Dual loop clock generator removes jitter and provides multiple high frequency outputs

As the speed and resolution of data converters continue to increase, so does the need for higher frequency sampling clock sources with lower phase noise. The integrated phase noise (jitter) of the clock input is one of the many performance bottlenecks that designers face when designing cellular base stations, military radar systems, and other designs that require high-speed and high-performance clock signals. Ordinary systems have multiple low frequency noise signals that the PLL can upconvert to higher frequencies to clock these devices. A single high frequency PLL can solve the frequency conversion problem, but it is difficult to design a PLL with a loop bandwidth low enough to filter out high noise reference effects. A PLL with low-frequency, high-performance VCO/VCXO and low loop bandwidth clears the high-noise reference but does not provide high-frequency output. High-speed and noise filtering can be achieved by combining two PLLs simultaneously: a low-frequency, narrow-loop bandwidth device (for clearing jitter), followed by a high-frequency device with a wide loop bandwidth.

Some modern dual-loop analog PLLs are integrated on a single chip, allowing designers to reduce low-frequency reference jitter while providing high-frequency, low-phase noise output. This saves valuable PCB board area and allows multiple devices at different frequencies to be clocked from the same phase-aligned source.

The AD9523, AD9523-1, and AD95244 clock generators (shown in Figure 1) consist of two series-connected analog PLLs. The first PLL (PLL1) clears the reference jitter and the second PLL (PLL2) generates the high frequency phase aligned output. PLL2 can also generate high fundamental frequencies, and then derive various low frequencies based on this. PLL1 uses an external low frequency VCXO and a partially embedded third-order loop filter to form a PLL with a loop bandwidth ranging from 30 Hz to 100 Hz. The bandwidth of this loop directly affects the amount of reference input phase noise that will propagate to the output. PLL2 uses an internal high-speed VCO (3.8 GHz center frequency, 3 GHz for the AD9523-1) and a partially embedded third-order loop filter with a nominal loop bandwidth of approximately 500 kHz. The bandwidth and phase noise of the internal VCO directly affects the wideband phase noise of the overall output.

Dual loop clock generator removes jitter and provides multiple high frequency outputs

Figure 1: Functional Block Diagram of the AD9523-1

Many engineers use dual-loop PLLs as frequency converters to reduce a fixed amount of reference input jitter, but more accurately it is considered a low phase noise frequency converter whose performance is limited by the loop bandwidth of each PLL and the VCO/ The effect of the phase noise curve of VCXO.

The ADIsimCLK simulation tool provides an easy way to determine the effect of reference phase noise on the phase noise of a dual-loop PLL output. This example uses ADIsimCLK to simulate the effect of a high noise reference on the overall phase noise of the AD9523-1. Figure 2 shows a typical phase noise curve for a simulated 122.88 MHz reference input.

Dual loop clock generator removes jitter and provides multiple high frequency outputs

Figure 2: Reference phase noise curve at 122.88 MHz

PLL1 relies on high performance VCXO and low loop bandwidth to attenuate reference phase noise, allowing the phase noise of the VCXO to dominate. This example uses a Crystek CVHD-950 VCXO to generate the same output frequency as the reference input. This plot directly compares the amount of reference phase noise present at the output of PLL1. Figure 3 compares the phase noise curve of the Crystek CVHD-950 VCXO with the reference input phase noise.

Dual loop clock generator removes jitter and provides multiple high frequency outputs

Figure 3: Crystek CVHD-950 phase noise curve at 122.88 MHz


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