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Abstract: The SAA7110 is a programmable front-end video decoder from Philips that converts incoming video signals into YUV digital signals. The article introduces the main features, structure principle and pin function of SAA7110, compares the difference between SAA7110 and SAA7110, gives the key pins that should be paid attention to in the application, and finally introduces its application connection and an image acquisition system. Application structure.Key words: SAA7110; video decoding; image processing
The video decoder SAA7110 is a programmable front-end video decoder manufactured by Philips. Compared with the SAA7111, although some of the pin signals are similar, there are still big differences, and it needs to be given enough attention in practical applications. Most of the domestic video collection or image acquisition uses SAA7111, while the more SAA7110 mentioned does not see much information on it. In the production of products, only a few domestic companies (such as Beijing Jiaheng Zhongzi Image Technology Co., Ltd.) use the chip. Based on the needs of scientific research and practice, this paper elaborates on the main features, structural functions and pin applications of SAA7110.
1 Main features
The main features of the SAA7110 are as follows:
◠has 6 analog inputs (4 × CVBS, 3 × Y / C or a combination of the two);
â— With 3 analog processing channels;
â— Built-in 3-way anti-aliasing filter;
â— Add 2 channels of analog signals;
â— Includes 2 8-bit CMOS video A/D converters;
â— Program the selected CVBS/Y channel as static gain control or automatic gain control;
â— Can perform white peak control;
â— Brightness and chromaticity processing can be performed on PAL B/G, NTSC M, SECAM systems;
   ◠Full HUE control;
â— Automatic 50/60Hz field frequency detection and automatic conversion between standard PAL and NTSC, forced SECAM;
â— It can realize line and field synchronization detection for all standards;
â— For the PAL system, the UV signal delay line can be used to correct the phase difference of the chrominance signal;
â— YUV bus supports the following data rates:
—780×fh=12.2727MHz, 60Hz (NTSC);
—944×fh=14.75MHz, 50Hz (PAL/SECAM);
â—The data output format is YUV 4:1:1 (8bit) and YUV 4:2:2 (8bit);
â— User programmable brightness peak aperture correction;
â—All systems can use the same frequency circuit crystal oscillator (26.8MHz);
â— With real-time status information output (RTCO);
figure 2
   ◠Brightness, contrast, and saturation (BCS) control can be performed on the YUV bus;
â— The output pin has a user-programmable universal transfer switch;
â— The conversion between the clock generation circuit (CGC) and the external CGC (SAA7197) can be performed on the slice;
â—With power-on control function;
â— with a controllable I2C bus;
â— Compatible with the CCIR601 standard.
2 structure principle and pin function
2.1 Structural principle
The functional block diagram of the SAA7110 is shown in Figure 1. The function of the main part of the block diagram is explained below.
(1) Analog input processing
The SAA7110 has six analog signal inputs. The two analog main channels are composed of a clamp circuit, an analog amplifier, an anti-aliasing filter, and a video CMOS A/D converter. The other analog channel also contains clamp circuits, analog amplifiers, anti-aliasing filters, and can be added to or directly converted to two main channels before A/D conversion.
   (2) Analog control circuit
The clamp control circuit controls the correct clamping of the analog input signal. High frequency coupling capacitors are used to store and filter the clamping voltage. For luminance or CVBS signals, the usual digital clamp standard is 64 and the chrominance signal is 128. The gain control circuit generates the static gain standard of the three analog amplifiers through the bus, and can also control one of them through the built-in automatic gain control (AGC) circuit. The role of the AGC is to amplify the CVBS or Y signal to the desired signal amplitude to be the same as the ADC input voltage range. The anti-aliasing filter should be suitable for the clock frequency. A vertical blanking control circuit is used to generate a bus programmable vertical blanking pulse. Gain and clamp control are inactive during vertical blanking.
(3) Chromatic circuit
The 8-bit digital chrominance signal passes through the input interface and is reduced by the chrominance bandpass filter and then sent to the multiply input of the quadrature demodulator. In the two subcarrier signals from the local oscillator DTO1 (Discrete Time Oscillator), the phase shift of the subcarrier signal is 90°, and the frequency is determined by the color system of the currently input video signal. For all PAL and NTSC signals, the multiplier can be used as a quadrature demodulator; for SECAM signals, the multiplier is used as a down-converting mixer. After the two multiplied output signals are converted to a continuous UV data stream, they can be used in two low-pass filter stages before being applied to the gain controllable amplifier. The last multiplexed low pass filter will be used with the predecessor to set the required bandwidth. The PAL and NTSC raw signals flow into the comb filter. The SECAM raw signal is fed through a bell filter (center frequency of 0 Hz), a phase demodulator, and a differentiator to obtain a frequency-demodulated color difference signal. The SECAM signal is de-emphasized and fed into the cross-conversion to produce a continuously transmitted color difference signal. These signals are sent to the BCS (brightness, contrast, saturation) processing and they will eventually reach the output format level and the output interface. Figure 2 shows the working process diagram of the chrominance circuit.
(4) Brightness circuit
The 8-bit luminance signal (digital CVBS format or luminance format (S-VHS, HI8)) is fed through a transformable pre-filter. The enhancement of the high frequency component can compensate for the loss. Chroma traps (fc = 4.43 MHz or 3.58 MHz, center frequency selectable) eliminate most color carrier signals, so S-Video (S-VHS, HI8) signals must pass normally. The high frequency component of the luminance signal can be enhanced in two bandpass filters with optional transmission properties (increased sharpness is controlled by the I2C bus). The signal can be boosted again in the optional core circuit and then added to the original (unboosted) signal. The enhanced luminance signal is fed to the BCS control and output interface via variable delay.
(5) Digital YUV bus
Digital information can be transferred from the output interface to the field bank, digital color space converter (SAA7192 DCSC) or video enhanced analog-to-digital processor (SAA7165 VEDA2) via the 16-bit YUV bus. These outputs can be controlled by FEIN. The YUV data rate is equal to LLC2. The output signals Y7 to Y0 are bit bits of the digital luminance signal. The output signals UV7 to UV0 are bits of the multiplexed color difference signals (B to Y) and (R to Y). The time frame in the format table is the time required to transmit a full sample. This time frame can be controlled by the HREF signal. Fast enable is achieved by setting FEIN low. This signal can also be used to control the fast switching of the digital YUV bus. When the FEIN pin is high, the Y and UV outputs are forced to a high-impedance state.
(6) Synchronous processing
The currently filtered luminance signal is sent to the sync stage. The sync pulses are sent to the phase detector by singulation, where they are compared to the subdivided clock frequency and the result is output to the loop filter to store all phase difference information. The adjustable output signals HCL and HSY are generated by the requirements of the analog front end. The output signals HS, VS, PLIN are locked to the time reference mark to ensure that they are between the input signal and the HREF signal because further improvements in the circuit may change the overall processing delay and are not recommended for use in the input. Signal timing requirements are absolutely accurate. Driving a oscillator with a loop filter produces a line frequency control signal LFCO.
2.2 pin function
Figure 3 shows the pinout of the SAA7110. The functions of each main pin are as follows:
SP: Test input pin, (switching pin) This pin should be grounded during normal operation.
AP: Test input pin, (acting leg) should be grounded during normal operation.
RTCO: Real-time control output. This pin is used in conjunction with the HPLL, FSC-PLL increment and PAL or SECAM sequence information.
Figure 4
   SA: I2C bus slave address selection input. At low level, if the slave address is 9CH, it is written; if the slave address is 9DH, it is read. When it is high, it is written when the address is 9DH and read when 9FH.
SDA: I2C bus serial data input/output.
SCL: I2C bus serial clock input.
VDD, VSS: +5V power supply and ground.
AIXX: Analog input pin.
AOUT: Analog output pin.
LFCO: Line frequency control output pin; this analog clock signal can be used to drive an external CGC; its frequency is a multiple of the actual line frequency (7.375/6.13636MHz).
LLC: Line lock clock input/output pin. When CGCE is 1, this pin is output; when CGCE is 0, this pin is input).
LLC2: 2-way input and output of the line-locked clock; FLLC2=0.5fLLC. When CGCE is 1, the pin is the output; when CGCE is 0, the pin is high impedance).
CREF: Reference clock input/output pin (output when CGCE=1; input when CGCE=0).
RESET: Reset signal, active low.
CGCE: CGC enable input pin, when CGCE is 1, it is valid in slice CGC; when CGCE is 0, use external CGC mode, SAA7197 can be used.
HCL: Horizontal clamp input/output pulse, which can be programmed via the I2C bus PULIO bit: PULIO is 1 when output; PULIO is 0 when input. This signal can be used to indicate a high clamp time to the analog input interface. The start and end of the high level can be controlled by programming the I2C bus register (in output mode only).
HSY: Horizontal sync input/output, which can be programmed via the PULIO bit of the I2C bus: PULIO is 1 when output; PULIO is 0 when input. This signal can be sent to the analog interface. The start and end of the high level can be controlled by programming the I2C bus register (in output mode only).
HS: Horizontal sync output. Its positive slope position is programmable.
PLIN (HL): PAL does not output the identification pin. The demodulated PAL signal can send a line feed signal (PLIN=0) or a non-line feed signal (PLIN=1). After demodulating SECAM, the DR line signal can be sent (PLIN= 0) or DB line signal (PLIN = 1). The PLIN function can be selected by setting the RTSE of the I2C bus to 0 (H-PLL output lock; high level indicates that the internal PLL is locked); and the HL function can be selected by making the RTSE of the I2C bus 1 high.
ODD (VL): parity field output identification, high level represents odd field. The ODD function can be selected by setting the RTSE of the I2C bus to 0 (vertical output lock; high level means the internal VNL (vertical noise limiter) is locked); the RTSE of the I2C bus is 1 optional VL function.
VS: Vertical sync input/output (programmable by the OEHV bit of the I2C bus: output when OEHV is 1; input when OEHV is 0). This signal can be used to indicate vertical synchronization with the YUV output. At VNL, its high period is close to 6 lines. The positive slope includes the phase information of the deflection controller (such as the TDA9150). In input mode, this signal is used to synchronize vertical gain and clamp blanking, active high.
HREF: Horizontal reference output, which indicates that there is data on the digital YUV bus. A positive slope indicates the beginning of a new line of scan lines. Whether the high level of HREF is 768 Y sampling points or 640 Y sampling points depends on the field frequency (50/60 Hz). In addition, HREF can be used to synchronize data multiplexers or resolvers. During the vertical blanking signal, HREF also exists.
Y7～Y0: 8-bit brightness (Y) digital output. The SQPB by setting the I2C bus is part of an optional digital YUV bus (data rate LLC/2), or A/D2(3) output (data rate LLC/2).
UV7～UV0: 8-bit digital UV (color difference) output for outputting CVBS signal or multiplexed color difference signal of UV component after chrominance signal demodulation. The format and multiplexing mode can be selectively controlled by I2C bus. These signals can be selected as part of the digital YUV bus (data rate LLC/2) or A/D2(3) output (data rate LLC/2) by setting the SQPB of the I2C bus to 1.
FEIN (MUXC): Fast input enable signal (low active) that can be used to control fast switching of the digital YUV bus. Entering a high level causes the film's Y and UV outputs to become high impedance. Using this function requires the MS24, MS34, and MUYC of the bus to be deasserted (respectively component input; fast switching of the Y/C signal and the control signal of the analog multiplexer that locks the CVBS signal). If one of the MS24, MS34, MUYC is high, the FEIN will be automatically deasserted (the digital YUV bus is active).
GPSW (VBLK): Universal switch output, which can be programmed via bit 1 of 0DH on the I2C bus. The GPSW function (vertical blanking test output) can be selected by setting the VBLKA of the I2C bus to 0.
XTAL0: Crystal output (to 26.8MHz crystal); not used when using TTL clock.
XTAL1: Crystal input (26.8MHz crystal) or an external clock connected to the TTL square wave clock signal.
3 applications
3.1 Typical application
Figure 4 shows a typical application connection circuit for the SAA7110. As long as a video signal is input to the input of the SAA7110 in this circuit, digital signals of different formats can be obtained at the output. This circuit has important applications in analog-to-digital conversion of video processing.
3.2 PCI bus high speed video image capture card
The PCI bus is a high-performance local bus that supports 32-bit/64-bit data transfer and linear burst mode with a transfer rate of 133 Mbps. It supports plug-and-play and is ideal for image capture card design. In addition, PC video applications can be supported using the PCI bus port provided by Philips' SAA7146 desktop multimedia application chip (see related information). FIG. 5 is a schematic block diagram of a high speed video image acquisition system based on a PCI bus. The SAA7110 and SAA7146 are the backbone parts of the image acquisition card, and can realize high-speed data transmission with the PC through the PCI local bus. Here, the SAA7110 mainly performs sampling, quantization, and decoding processing on an analog video signal.
The main pins of SAA7146 used in the hardware design of this acquisition card are VS-A, VS-B, HS-A, HS-B, PXQ-A, PXQ-B, LLC-A, LLC-B, GPIO3∽0. Wait. At the same time, in the PCB layout, the SAA7146 should be as close as possible to the PCI socket to ensure normal operation. The main problems involved in software driver design are: use PCI BIOS to obtain the PCI configuration parameters of the capture card, apply for RPS physical space and image physical space, register assignment of SAA7146 and SAA7110 initialization, write SAA7146 to capture image RPS program interrupt service program, The interface between the driver and the application, etc. The author has used DDK to develop the driver to collect images under WIN98. The actual use proves that the captured image has a high resolution and the image is very clear, which can meet the actual needs.
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