Three energy-saving technologies using PCI Express IP

**Summary** The use of PCI Express (PCIe) in computing applications, such as servers, networking equipment, and laptops, has been widely adopted over time. Its application is also expanding to smaller, battery-powered devices like smartphones, tablets, and wearables. As data traffic increases in these environments, so do power requirements. This has driven designers to seek ways to reduce system-on-chip (SoC) power consumption during low-activity or idle periods. Battery-powered devices often operate in idle or deep sleep modes, but these modes come with a trade-off: longer recovery times when returning to normal operation. For PCIe IP integration into SoCs, energy-saving technologies from the protocol and advanced power management techniques can help control power consumption. Clock gating reduces dynamic power, while power gating is more effective for static power reduction. However, in deep power-saving modes, power-gated PCIe IP typically requires link retraining, which increases recovery time—making it a significant challenge. This article explores three energy-saving techniques using PCIe IP and how designers can leverage protocol-based power management features and design tools to create energy-efficient SoCs that support fast recovery. **1. Clock Gating Technology: Comprehensive Tools** Modern synthesis tools offer various clock power management techniques, including traditional clock gating and self-gating. In traditional clock gating, the tool identifies conditions and combines them to generate a clock enable (EN) signal that disables the clock-to-trigger path. An integrated clock gating (ICG) unit uses this EN to turn off clocks for a series of flip-flops. Self-gating works by checking if the input to a flip-flop remains unchanged, then disabling the clock based on the XOR of the input and output. These strategies improve energy efficiency, though they may slightly increase area due to added logic. Synthetic tools often apply self-gating after traditional clock gates to further optimize power savings. Automated analysis using power tools helps evaluate and refine clock gate performance, identifying opportunities for improvement. On 28nm technology, optimized clock gating can achieve at least 40% energy savings and reduce area by about 9%. Self-gating after traditional clock gates can cut energy use by 5% and increase area by 1%. At 16nm FinFET nodes, integrated clock gating (traditional + self-gating) achieves 25% energy savings. **2. Clock Gating Technology: PCIe IP** While tool-based clock gating reduces power, it may not fully consider the design-level implications. Traditional clock gating only affects flip-flops, but the clock tree—comprising drivers and gating units—can consume up to 25% of standby power in complex designs. Turning off the clock at the root level can significantly reduce power consumption, requiring architectural decisions. Consider a PCIe IP design with three clock domains: AMBA master, AMBA slave, and core. Depending on the request direction, different clocks can be turned off. For example, when inbound requests are processed, the AMBA slave clock can be disabled. Similarly, outbound requests allow the AMBA master clock to be turned off. These optimizations can save at least 10% power and improve standby efficiency. **3. Clock Gating and Power Gating: PCIe Protocol** The PCIe protocol defines power states like L0, L1 (sub-states), and L2/L3. Exiting L2 and L3 involves link retraining, leading to longer recovery times. In L0 and L1, clock gating minimizes recovery time. For instance, in L1, the reference clock may not be needed, allowing the local core clock to be turned off without stopping the PLL. In L1.1, the PLL and transmitter/receiver can be disconnected, achieving up to 97.5% energy savings. In L1.2, even the common mode voltage can be turned off, reducing power to 0.05%. PCIe also supports message-based power management features like Delay Allowed Notification (LTR) and Optimized Buffer Clear/Complete (OBFF). LTR allows downstream devices to inform the host of maximum allowable delay, helping software manage recovery times. OBFF enables efficient scheduling, allowing systems to stay in power-saving modes longer. **Conclusion** Power management is critical for devices with sporadic communication and fast recovery needs. Tool-based and protocol-based clock gating techniques maximize energy savings in PCIe IP designs. Clock gating is ideal for near-zero recovery times, avoiding link retraining and saving power. Synopsys’ DesignWare IP solution for PCIe includes structured clock gating blocks, support for L1 substates, power gating solutions, and features like LTR and OBFF. It supports all PCIe power management features, ensuring energy-efficient SoC designs. For more information, visit: [https://Company/Publications/DWTB/Pages/dwtb-L1-substate...](https://Company/Publications/DWTB/Pages/dwtb-L1-substate...)

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