Abstract: DaVinci technology is the industry's first comprehensive solution portfolio that integrates DSP processors, software, tools and technical support, making it ideal for developing optimized digital video terminal equipment. This paper introduces a digital video system design based on DaVinci technology. The overall architecture, video part functions, power supply design and software implementation of the system are elaborated.
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introduction
Nowadays, digital video innovation has become a hot spot in the digital information industry. The design method of digital video system is constantly improving, and the complexity of digital video system is far more than ever. DaVinci technology's successful implementation of digital video requires the latest advances in four elements: processors, development tools, software, and system expertise. With digital video, audio, voice and voice technology in a platform that integrates these four elements, DaVinci technology can lay the foundation for the current revolution in digital video.
This design is to complete the acquisition, processing and display of video on a 60*60mm PCB. The video image captured by the camera is converted to a format that the DaVinci processor can process via the decoder, and H.264 and MPEG-4 codecs are implemented in the Codec Engine, which can reach up to 1280*720 resolution on the LCD screen. 30fps (frames per second) is displayed smoothly. Such a digital video system can achieve the advantages of small size, strong function, flexible design and wide practicality.
1. 1. The overall architecture and working principle of the system
2. 1.1 TMS320DM6446 device The DaVinci processor TMS320DM6446 is based on the industry's highest performance DSP platform - TI TMS320C6000TM by ARM926EJ-S core, TMS320C64x+ DSP core, system control, video processing subsystem (VPSS), power management, external memory Interface modules, peripheral control modules and other functional modules.
The ARM926EJ-S core in the TMS320DM6446 has 16KB instructions and 8KB data cache with 16KB ROM and 16KB RAM. The TMS320C64x+ DSP core has 32KB L1 program RAM / C ache , 80 KB L1 data RAM / Cache and 64KB L2 RAM / Cache. DDR2 memory controller; 64-channel enhanced DMA controller; serial port (3 UART, I2C, SPI, audio serial); 3 64-bit general-purpose timers; 10/100M Ethernet; USB2.0 port; PWM ports; up to 71 general purpose I/O ports; support for MMC/SD/CF cards, etc. The system control module provides a watchdog, interrupt controller, power management controller, reset controller and two on-chip oscillators. Video Processing Subsystem (VPSS) has a Video Front End Input (VPFF) interface for video input consisting of a CCD controller (CCDC), preprocessor, columnar module, auto exposure/white balance/focus module (H3A) and registers; The Video Back-End Output (VPBE) interface for video output consists of an on-screen menu regulator (OSD), a video encoder (VENC), and four 10-bit DACs.
1.2 System hardware composition and working principle
The entire digital video system uses a solution from the DaVinci processor (TMS320DM6446), DDR2 SDRAM, NAND FLASH, video decoder TVP5146, power management chip TPS65023, LTC3412 plus peripheral interface chip. The video decoder performs analog-to-digital conversion of the analog video signal transmitted from the CCD camera into a digital video signal conforming to the ITU-BT.656 standard, and then transmits the digital video signal to the front end of the video processing subsystem of the Finch processor. The pre-processing is sent to the back end of the video processing subsystem through the Codec Engine codec, and the digital video signal is directly output to the display terminal or the analog video output of the NTSC/PAL system is provided through four 54 MHz DACs. The ARM terminal on the DM6446 is mainly used as a controller to control the video decoding chip and the peripheral interface chip. The DSP terminal is mainly responsible for video encoding and decoding. System hardware block diagram shown in Figure 1.
Figure 1 system hardware block diagram
1. 2. The hardware structure of video part and its analysis
2. 2.1 Video Acquisition and Decoding
This design uses TI's video decoding chip TVP5146 to complete the conversion from analog to digital video. The TVP5146 allows 10 analog video inputs with 4 10bit A/D converters; the field sync signal VS, the line sync signal HS, the even and even field signal FID, and the clock output signal DATACLK are all directly derived from the pins, eliminating the need for a synchronous clock circuit. the design of.
Y[9:2] on TVP5146 is the output luminance video signal, DATACLK is the output clock of the line lock system, the pixel clock frequency is 27MHz, used for synchronous data acquisition, HS is the line synchronization signal, and VS is the field synchronization signal respectively. The signals corresponding to the DaVinci processor DM6446 video port are connected. The high level of HS indicates the number of valid sampling points, and the high level of VS indicates a valid signal. For NTSC signals, the single field is 243 lines. When the parity field signal FID is "1", it indicates that the current field is odd. , "0" means even field. The interface circuit between the video decoder chip and the DM6446 is shown in Figure 2.
Figure 2 video front-end module interface
2.2 Image Processing and Display
The difficulty in designing a real-time image processing system is how to process a large amount of image data in a limited time. Real-time effects can only be achieved when the processing speed of the image processing system reaches 25 frames per second or more. The most important thing to display high-definition images on the display terminal is the video codec operation in Codec Engine. The DaVinci processor can achieve high-definition video output through a variety of complex video codecs, such as MPEG-4 codec can display 30fps resolution of 720p (1280 * 720); H.264 codec can display 30fps resolution For D1 (720*480) and so on. The online video display processor provided by the video backend in the TMS320DM6446 processor video processing subsystem can display two separate video windows or two separate OSD windows, as well as a video window, an OSD window and a property window. The form is displayed. After the video encoder encodes the image data, it can directly output the digital video signal to the liquid crystal display through the internal LCD controller. It can also perform D/A conversion through four 54MHz DACs to provide NTSC/PAL, S-video and other formats. Video or audio output.
3. Power supply design
This design uses TI's latest DaVinci technology-based TMS320DM644x DSP power management chip TPS65023 to achieve high-performance CNC functions and efficiency in the widest load current range up to 1.5A. The TPS65023 integrates three buck converters to support the system's core voltage, peripherals, I/O, and memory voltages. It also integrates two general-purpose 200mA linear low-dropout (LDO) regulators that can be enabled by external input pins. Each LDO has an input voltage range of 2.5 V to 6.5 V, so it can be powered by one of the integrated buck converters or directly from the battery.
In this design, the VDCDC1 pin of the TPS65023 outputs 1.2V for the core supply of the DM6446, the VDCDC2 pin outputs 1.8V for the DM6446 memory interface, and the VDCDC3 pin outputs 3.3V for the DM6446 peripheral interface. . Since the TPS65023 only provides 1A/1.8V voltage for two DDR2 SDRAMs, an output 1.8V power management chip is required to power the DDR2. The LTC3412A output current is 3A. This allows the system to be powered by two power management chips. The interface circuit between TPS65023 and DaVinci DM6446 is shown as in Fig. 3.
Figure 3 Interface circuit of TPS65023 and DM6446
4. Software Implementation
The DaVinci software architecture covers low-level OS drivers and even application APIs. In the DaVinci software platform, it can be subdivided into multi-task CODECs, namely Video, Image, Speech, and Audio, collectively called VISA. It also includes a CODEC engine remote server with a multimedia framework component. The resulting Signal Processing Layer (SPL) is connected to the Application Layer (APL) via the VISA API interface and to the underlying core via DSP/BIOS. APL includes customer value-added differentiated design software modules and communicates with many peripheral interface drivers of the underlying kernel through the Linux API.
The use of the eXpressDSP configuration tool makes the process of configuring a CODEC extremely simple. Here is a complete application development step:
The first step is to develop and complete Codec. It is to open the core algorithm of pronunciation video encoding and decoding. It is packaged into Codec library according to xDM standard. Codec mainly completes the core algorithm of audio and video. The application is called when it runs, and does not participate in other functions.
In the second step, Codec is integrated into Codec Engine. Integrate the first-developed Codec or the existing xDM-compliant Codec into Codec Engine. This step requires configuring two JavaScript script files. One of the script files indicates the usage and configuration information of Codec. For *.cfg, the other describes the configuration of Codec's memory allocation on DaVinci. The file name is usually *tcf. After configuring these two files, use the make command to generate Codec Engine. The file name is generally *.X64P. Can be called directly by the application.
The third step is to open the pronunciation video application and call Codec Engine in it. Open a pronunciation video application under Linux, including user interface, audio and video capture, playback, synchronization, etc., in which the call to Codec Engine is completed, the application also needs to complete a script configuration file with the extension cfg to indicate to Codec The usage of the Engine.
The fourth step is to load the DSPLINK and CMEM modules and run the application. A complete DaVinci audio and video application is completed. Many of the processes are completed through script file configuration. The process is very simple and easy to understand. To run it on Finch, first load the DSPLINK and CMEM driver modules. DSPLINK mainly implements the underlying communication of arm and dsp, while CMEM mainly completes the function of allocating contiguous memory on the physical segment. Two modules so that you can run the completed application directly.
5. in conclusion
The digital video system based on TMS320DM6446 as the core processor has been realized and powerful, stable performance, strong scalability, low power consumption, and can accelerate digital video innovation. The innovations of this paper: 1. Based on TI's powerful DaVinci processor (dual core), it can realize complex codec such as H.264. 2. Powered by TI's power management chip TPS65023, which is powered by DaVinci, to solve interference, EMI/EMC problems and achieve low power consumption.
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