A typical video processing system uses a microprocessor to control a video pipeline that includes a video source and sink, a large memory for storing video data, and a video processing system (Fig. 1).
When implementing and debugging various video algorithms, you need to verify their functionality through software and hardware emulation. The real-time nature of the video stream and the large amount of video data required per frame make the simulation of video processing applications a particular challenge.
Design environment
The Video Basic Suite (VSK) supports the rapid development and debugging of high-performance video processing systems for a wide range of video applications. VSK uses the Xilinx® Virtex-4 XC4VSX35 device, which is optimized for DSP processing with a high percentage of multiply-accumulate blocks (also known as DSP48) in the fabric, and is supported by a rich set of video interface features such as DVI and VGA. , component (HD), composite, S-video and SDI.
In general, developing video algorithms requires hardware to perform video operation verification on real-time data streams, and a simulation environment is required to develop and test video processing components. VSK provides both software emulation and real-time operation for each component of the video system, allowing you to develop video IP (including filters, video block sets, accelerators, and video interface conversions) or final applications such as codecs, image enhancements. , dynamic gamma correction and motion estimation. Integration with the tool suite and I/O diversity enable quick and easy introduction of video onto the board and optimize its running algorithms.
Also available with VSK are reference designs, some of which are written in HDL and others built using the Xilinx System Generator for DSP design environment. To remove the complexity of introducing data through various video interfaces and sending them to Virtex-4 devices, we have a library of video interface block sets that allow all interface block sets to be controlled by a MicroBlaze controller.
To highlight some of the capabilities of VSK, I will explain the MPEG-4 Part 2 decoder demo design.
MPEG-4 Part 2
The MPEG-4 Decoder Demonstration System consists of an FPGA hardware evaluation platform, Xilinx IP cores, and embedded software that together perform decompression of industry standard encoded video bitstreams.
For this design, the FPGA is programmed to perform decompression and drive video display. A Compact Flash card is used to hold multiple compressed video streams and FPGA configuration bitstreams. An embedded processor in the FPGA reads the bitstream from the Compact Flash card, writes it to an external DDR memory, and sends it to the MPEG-4 Part 2 decoder. The decoder's output is then reformatted to the video standard to be displayed on the external monitor via the video I/O daughter card.
The system overview is shown in Figure 2. The MPEG-4 decoder core, DDR memory controller, color space converter, VGA interface, macroblock format converter, and MicroBlaze soft core processor and related peripheral circuits are implemented in the XC4VSX35 FPGA. ZBT memory, DDR memory, System ACE technology, Compact Flash connectors, two-wire LCD displays, and a digital-to-analog converter are all located on the hardware platform.
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Embedded processor
Video systems generally require a control processor. The processor is typically used to communicate with the host system, establish video processing operations, calculate coefficients, and typically operate as a low rate data processor. VSK's video standards with input and output sources, combined with System Generator hardware co-simulation capabilities, allow you to quickly test and debug your system with real-time video streaming.
In this MPEG-4 demo design, the embedded MicroBlaze processor acts as an overall system-level controller that handles functions such as the user interface, reads the compressed bit stream from the Compact Flash card, and sends the bit stream to the MPEG-4 decoder. Core, and monitor all system status flags, etc.
The Xilinx System Generator for DSP greatly simplifies the design process for integrating MicroBlaze processors into the framework. You can use Xilinx System Generator and Embedded Development Kit (EDK) software tools to implement and simulate a system with one processor and FPGA video processor function that operates on live video streams. System Generator automatically generates software drivers to support reading and writing of data designed for System Generator. Both methodologies currently support the integration of a MicroBlaze controller:
The System Generator design is exported to the EDK system. When used in pcore (processor core) export mode, the memory map block and all other blocks are encapsulated into a pcore peripheral. Software drivers and documentation for the memory mapped interface are also generated and provided with the peripheral.
The EDK project is imported into the System Generator design for hardware co-simulation. When used in EDK import mode, import an EDK file into System Generator by running the EDK Import Wizard. When the import wizard is complete, the EDK system is pulled into the System Generator design like a black box. During the import process, the EDK system is extended through the Fast Simplex Link (FSL) interface, which is used to communicate with the memory map.
Hardware co-simulation
Watching the final output video is an important quality measure for all video systems. VSK's input and output source video standards, combined with System Generator hardware co-simulation capabilities, allow you to quickly test and debug your system with real-time video streaming.
System Generator provides a hardware co-simulation interface that compiles a System Generator graph into an FPGA bitstream and associates the bitstream with a new runtime hardware co-simulation block. When the design is simulated in Simulink, the results of the compilation part are calculated by hardware rather than software.
System Generator provides a high-speed hardware co-simulation interface that allows Simulink vector or matrix signals to be read or written to the FPGA hardware in a single transaction. By using these interfaces, you can greatly reduce the number of PC/hardware transactions during the simulation process, further speeding up the simulation beyond the speed of traditional hardware co-simulation. Utilizing the popularity and advancement of Ethernet technology, this interface provides a convenient and high-bandwidth co-simulation method for external FPGA devices.
VSK supports two Ethernet co-simulation modes:
The network-based Ethernet hardware co-simulation interface provides co-simulation access through the IPv4 network infrastructure to the FPGA platform. Due to the wide distribution of IPv4 networks, this interface provides a way to communicate directly with remote hardware connected to a wired or wireless network. This interface is especially useful for remote FPGA platforms (such as cross-office or international), or where multiple designers must share a single development board. The network-based Ethernet interface supports operation in 10/100 Mbps half/full duplex mode.
Peer-to-peer Ethernet hardware co-simulation provides a co-simulation interface over the original Ethernet connection. The raw Ethernet connection refers to a Layer 2 (data link layer) Ethernet connection between a supported FPGA development board and a PC host with no routing network devices along the way. The point-to-point Ethernet interface supports working in 10/100/1000 Mbps half/full duplex mode. A huge framework for Gigabit Ethernet connectivity is also supported as long as the underlying connectivity is supported.
VSK includes software, hardware, cameras, cables and a detailed user guide and reference design. It includes a limited version of System Generator for DSP, ISE® software, and Embedded Design Suite (EDK) FPGA design tools, as well as a Xilinx ML402-SX35 development board, video I/O daughter card (VIODC), CMOS Image sensor camera, power supply and cable.
in conclusion
With this complete and easy-to-use solution, the Video Basic Suite is an ideal hardware platform to evaluate Xilinx FPGAs as a broad video and imaging application. With full integration and support of Xilinx System Generator for DSP software, VSK can take advantage of the new high-speed Ethernet hardware co-simulation capabilities for real-time system integration, development and verification of codecs, IP and video algorithms.
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