[Photo] MC145152 frequency synthesizer and its application

1 Overview

MC145152 is a large-scale integrated circuit produced by MOTOROLA. It is a dual-mode CMOS-LSI phase-locked loop frequency synthesizer that is set by half-line code input and programmed by 14 parallel input data. Its internal composition block diagram is shown in Figure 1. As shown. The chip contains a reference frequency oscillator, a reference frequency divider (12 × 8ROM reference decoder and 12bit ÷ R counter) for user selection, a phase detector with dual-end output, control logic, and 10-bit programmable 10bit ÷ N counter, 6-bit programmable 6bit ÷ A counter and lock detection etc. Among them, 10bit ÷ N counter, 6bit ÷ A counter, analog control logic and external dual-mode prescaler form the swallow pulse program divider, the total frequency division ratio of the swallow pulse program divider is: D = VN + A.

2. Pin arrangement and function

The pin arrangement of MC145152 is shown in Figure 2. It adopts 28-pin DIP package, and the functions of each pin are as follows:
Pins 4, 5, and 6 (RA0, RA1, and RA2) are reference address code input terminals, which are used to select the division ratio of the reference divider. Programming through 12 × 8ROM reference decoder and 12bit ÷ R counter. There are 8 options for frequency division ratio, and the relationship between its reference address code and frequency division ratio is listed in Table 1.
Pins 26 and 27 (OSCIN, OSCOUT) are the reference oscillator. When a parallel resonant crystal is connected to the two pins, a reference frequency oscillator is formed. However, a frequency setting capacitor (generally around 15pF) should be connected between OSCIN to ground and OSCOUT to ground. OSCIN can also be used as an input for external reference signals.
Pin 1 (VCO) is the input signal terminal, and the input signal is AC coupled to this pin, and its input signal frequency should be less than 30MHz.
Pins 10, 21 to 25 (A5 to A0) are the frequency dividing end of the 6bit ÷ A counter. The preset number determines the ÷ V / (V + 1) dual-mode pre-frequency device ÷ V / (V + 1) times.
Pins 11 ～ 20 (N9 ～ N0) are the frequency dividing end of 10bit ÷ N counter.
Pins 7 and 8 (φV, φr) are dual output terminals of the phase detector, which are used to output loop error signals. If the phase of fV> fr or fV leads fr, then φV becomes low and φr is still high; if fV Pin 9 (MC) is the mode control terminal, and the output mode control signal is added to the dual-mode frequency divider to realize the mode conversion. At the beginning of a counting cycle, "MC" is at a low level until the A line is full of its programmed value. Then, "MC" jumps to a high level and remains until the ÷ N counter is full The remaining value (NA). After the N counter is full, "MC" is reset to low, the two counters are preset to their respective programmed values, and the above process is repeated.
Pin 28 (LD) is the lock detection terminal, which is used to lock the output signal. When the loop is locked (that is, φV and φr are at the same frequency and in phase), the signal is high; when the loop is unlocked, LD is low.

3. Application examples

Figure 4 is a part of the circuit designed and developed for the railway dedicated 150MHz ultrashort wave interference directional instrument, in which the frequency of the voltage controlled oscillator output in the FM receiver MC3363 is pre-divided by the dual-mode prescaler MC12017, and then output to the programmable parallel input lock In the phase loop MC145152, the single-chip AT89C51 programs the MC145152 through the I / O port to change the initial value of its counter, thereby changing the frequency division ratio. The error signals φV and φr output from the dual output terminals of the phase detector are input to the LM358 One-stage double-ended active low-pass filter, among which R10, R18, R12, C16, etc. constitute the RC low-pass link of the active filter input circuit, and R11, C17 constitute the high feedback link of the active filter. The peak detector composed of D1 and C14, R9, C15 network further smoothes the error voltage output by the active filter, and directly controls the voltage-controlled oscillator in the MC3363, forming a complete numerical control phase-locked loop. The single-chip microcomputer receives the values ​​manually adjusted and set, and presets the initial count value of the MC145152 counter differently to lock different frequencies and achieve the purpose of changing signals at different frequency points. The signal corresponding to the frequency point is A / D to the single-chip microcomputer, and then input into the character display to display the signal field strength.